Stochastic Computing Convolutional Neural Network Architecture Reinvented for Highly Efficient Artificial...

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Stochastic computing (SC) is well-studied for AI edge computing on ASICs, particularly for CNNs.
• Optimization of SC for FPGAs is lacking, hindering efficient scaling and bitstream aggregation.
• Existing SC approaches face challenges in FPGA implementation and performance scaling.

Purpose of the Study:

• To develop FPGA-efficient 8-bit SC CNN computing architectures.
• To implement a fully parallel CNN model on Kintex7 FPGA using novel SC designs.
• To evaluate the performance, accuracy, and energy efficiency of the proposed SC CNN on FPGAs.

Main Methods:

• Reinvention of FPGA-efficient SC architectures: SC multiplexer multiply-accumulate, multiply-accumulate function generator, and binary rectified linear unit.
• Implementation of a fully parallel CNN model on Kintex7 FPGA.
• Evaluation of accuracy, energy saving, and data throughput compared to binary computing.

Main Results:

• Achieved minimal accuracy loss (0.14%) on the MNIST classification task compared to binary computing.
• Demonstrated at least 99.72% energy saving per image feedforward.
• Obtained 31x higher data throughput than modern hardware.
• Early decision termination enabled exponential performance gains with negligible accuracy loss.

Conclusions:

• FPGA-efficient SC CNNs are highly promising for AI edge computing, especially for classification tasks.
• The proposed SC hardware offers substantial energy savings and throughput improvements.
• SC's inherent noise limits its applicability to regression tasks, making it unsuitable for such applications.