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Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip

Marc Majoral¹, Javier Arribas¹, Carles Fernández-Prades¹

¹Centre Tecnològic de Telecomunicacions de Catalunya (CTTC/CERCA), Parc Mediterrani de la Tecnologia, Building B4, Av. Carl Friedrich Gauss 7, 08860 Castelldefels, Spain.

Sensors (Basel, Switzerland)

|March 13, 2024

Summary

This study introduces an affordable, high-sensitivity Global Navigation Satellite System (GNSS) receiver capable of tracking weak Galileo signals. The novel System-on-Chip Field-Programmable Gate Array design enables robust performance in challenging, low signal-to-noise environments.

Keywords:

FPGA GNSS SoC-FPGA high-sensitivity GNSS receiver software-defined radio system on chip

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Area of Science:

Electrical Engineering
Satellite Navigation Systems
Signal Processing

Background:

Traditional Global Navigation Satellite System (GNSS) receivers struggle with weak signal acquisition, particularly in challenging environments with high signal attenuation.
Advancements in GNSS signal processing algorithms are crucial for improving receiver performance and expanding application areas.
The integration of Software Defined Radio (SDR) concepts with hardware acceleration offers a promising path for developing more efficient and adaptable GNSS receivers.

Purpose of the Study:

To design and implement an affordable, real-time High-Sensitivity (HS) GNSS receiver.
To specifically enable the capture and tracking of weak Galileo E1b/c signals.
To provide a platform for research into advanced GNSS signal processing algorithms in low signal-to-noise environments.

Main Methods:

Utilized System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, merging SDR flexibility with FPGA hardware processing.
Developed a modular GNSS baseband processing engine within the SoC-FPGA architecture.
Tested the receiver with live Galileo signals under various signal strength conditions.

Main Results:

Demonstrated the receiver's capability to acquire and track weak Galileo E1b/c signals.
Achieved successful navigation solutions even at a carrier-to-noise density ratio (C/N0) as low as 20 dB-Hz.
Showcased enhanced power efficiency compared to conventional processor-based designs.

Conclusions:

The developed HS GNSS receiver is a viable, low-cost solution for research in advanced signal processing.
The SoC-FPGA architecture provides a power-efficient and adaptable platform for embedded software-defined receivers.
This work facilitates the development, testing, and validation of experimental GNSS signal processing techniques in challenging environments.