A Fast Transient Response Capacitor-Less LDO with Transient Enhancement Technology

Area of Science:

• Integrated Circuit Design
• Analog Electronics
• Power Management

Background:

• Traditional low-dropout regulators (LDOs) often require large on-chip capacitors for stability, increasing area and cost.
• Achieving fast transient response in LDOs without external capacitors is a significant challenge in modern integrated circuits.

Purpose of the Study:

• To propose a novel capacitor-less low-dropout regulator (CL-LDO) with fast transient load response.
• To ensure steady-state performance and loop stability without relying on off-chip or large on-chip capacitors.

Main Methods:

• Design of a CL-LDO using a rail-to-rail input and push-pull output (RIPO) amplifier for enhanced gain and low power consumption.
• Integration of a super source follower buffer (SSFB) with internal stability for robust loop performance.
• Inclusion of an auxiliary circuit to improve transient response without affecting steady-state stability.

Main Results:

• The proposed CL-LDO achieves a quiescent current of 47 µA and excellent load regulation of 25 µV/mA for currents from 0 to 20 mA.
• Demonstrated fast settling times: 0.2 µs for load steps from 0 mA to 20 mA and 0.5 µs for load steps from 20 mA to 0 mA.
• The design operates in a 180 nm process, converting 1.2 V–1.8 V input to 1 V output.

Conclusions:

• The proposed capacitor-less LDO effectively enhances transient performance while maintaining steady-state stability.
• This design offers a viable solution for power management in digital-analog hybrid circuits where space and efficiency are critical.
• The novel RIPO amplifier and SSFB contribute to achieving high performance without external compensation components.