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Frequency response analysis in electrical circuits provides vital insights into a circuit's behavior as the frequency of the input signal changes. The transfer function, a mathematical tool, is instrumental in understanding this behavior. It defines the relationship between phasor output and input and comes in four types: voltage gain, current gain, transfer impedance, and transfer admittance. The critical components of the transfer function are the poles and zeros.
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Related Experiment Video

Updated: Jun 29, 2025

Tuning a Parallel Segmented Flow Column and Enabling Multiplexed Detection
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PaCHNOC: Packet and Circuit Hybrid Switching NoC for Real-Time Parallel Stream Signal Processing.

Peng Hao1, Shengbing Zhang1, Xinbing Zhou2,3

  • 1School of Computer Science, Northwestern Polytechnical University, Xi'an 710072, China.

Micromachines
|March 28, 2024
PubMed
Summary

PaCHNOC, a hybrid network-on-chip (NoC), efficiently handles both long and short data packets for real-time embedded digital signal processor (DSP) systems. This novel approach significantly reduces latency, proving optimal for 5G base station subsystems.

Keywords:
hybrid NoCnetwork on chip (NoC)real-time processing

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Area of Science:

  • Computer Engineering
  • Embedded Systems
  • Telecommunications

Background:

  • Real-time heterogeneous parallel embedded digital signal processor (DSP) systems demand ultra-low latency network-on-chip (NoC) solutions for efficient data stream processing.
  • Existing Packet Circuit Switched Network-on-Chip (PCCNOC) excels with long data packets but incurs significant routing delay for short configuration packets.

Purpose of the Study:

  • To develop a novel hybrid NoC architecture, PaCHNOC, that addresses the latency challenges associated with transmitting both long and short data packets in embedded DSP systems.
  • To evaluate the performance of PaCHNOC in real-time heterogeneous parallel embedded DSP applications, specifically targeting 5G base station subsystems.

Main Methods:

  • Introduced PaCHNOC, a hybrid NoC architecture combining circuit switching for long data packets with routing-based transmission for short data packets.
  • Simulated PaCHNOC performance against existing NoC solutions for embedded DSP systems.
  • Implemented and tested PaCHNOC in a real 5G base station baseband subsystem.

Main Results:

  • PaCHNOC demonstrated a 65% overall latency reduction compared to related works in simulations for embedded DSP systems.
  • The PaCHNOC architecture effectively integrates short data packet transmission within the routing process, bypassing setup delays.
  • Deployment in a 5G base station baseband subsystem resulted in a 31% comprehensive latency reduction.

Conclusions:

  • PaCHNOC is a highly effective hybrid NoC solution for real-time heterogeneous parallel embedded DSP systems, significantly reducing latency.
  • The PaCHNOC architecture offers a superior approach for handling diverse data packet types in demanding applications.
  • PaCHNOC is validated as an optimal NoC for 5G base station baseband subsystems, enhancing overall system performance.