Optimizing FPGA implementation of high-precision chaotic systems for improved performance

Area of Science:

• Digital hardware implementation of chaotic systems.
• Field-Programmable Gate Array (FPGA) core development.

Background:

• Chaotic systems-on-a-chip offer significant potential for secure communication, data encryption, and random number generation.
• Digital implementations of chaotic systems require high performance in speed, complexity, and precision.

Purpose of the Study:

• To develop high-speed FPGA cores for chaotic systems, specifically the Lorenz system.
• To implement numerical integration techniques for sixth-order chaotic equations with high precision.

Main Methods:

• Developed FPGA cores using numerical integration techniques for chaotic systems.
• Analyzed and evaluated cores based on algorithm complexity, precision, hardware area, throughput, power consumption, and operational frequency.
• Validated designs through simulations and comparisons with existing literature.

Main Results:

• Achieved highly efficient sixth-order Lorenz discretizations with 3.39 Gbps throughput and 16-bit precision.
• Obtained 21.17 Gbps throughput with 64-bit precision for first-order implementation.
• Demonstrated benchmark performance surpassing similar investigations.

Conclusions:

• Successfully created high-performance FPGA cores for chaotic systems.
• The developed cores offer superior throughput and precision, setting new benchmarks in the field.
• These advancements are crucial for next-generation secure communication and data processing systems.