Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration

Area of Science:

• Neuromorphic computing
• Artificial Intelligence hardware
• Deep learning accelerators

Background:

• Neuromorphic processors offer potential for low-latency and energy-efficient AI processing using brain-inspired designs.
• Current neuromorphic solutions face challenges in matching conventional deep learning accelerators' performance and efficiency.
• Key challenges include reducing event-driven processing overhead and improving near/in-memory computing mapping efficiency.

Purpose of the Study:

• To address the performance and area efficiency limitations of current neuromorphic processors.
• To optimize event-based neural network inference on the SENECA neuromorphic architecture.
• To propose novel techniques for enhancing energy efficiency, latency, and area efficiency.

Main Methods:

• Comprehensive design space exploration for neuromorphic architectures.
• Development of spike-grouping technique to reduce energy and latency in event-driven processing.
• Introduction of event-driven depth-first convolution for improved area efficiency and latency in CNNs on neuromorphic processors.

Main Results:

• Optimizations achieved 6×–300× improvement in energy efficiency compared to state-of-the-art neuromorphic processors.
• Latency was improved by 3×–15×, and area efficiency by 3×–100× across various tasks.
• Demonstrated effectiveness on keyword spotting, sensor fusion, digit recognition, and high-resolution object detection.

Conclusions:

• The proposed optimizations significantly enhance the performance and efficiency of event-based neural network inference on neuromorphic hardware.
• Spike-grouping and event-driven depth-first convolution are effective strategies for overcoming current neuromorphic processing challenges.
• These optimizations show potential for generalization across a wide range of event-based neuromorphic processors.