Flare: An FPGA-Based Full Precision Low Power CNN Accelerator with Reconfigurable Structure

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Convolutional Neural Networks (CNNs) offer significant advancements but face challenges in computational demand and power consumption for low-power applications.
• Existing CNN accelerators, often based on High-Level Synthesis (HLS), struggle with efficient Field-Programmable Gate Array (FPGA) resource utilization and full-precision computations.

Purpose of the Study:

• To develop a dedicated CNN accelerator that addresses the limitations of current approaches, enabling efficient deployment in power-constrained environments.
• To enhance the utilization of FPGA computational resources and support full-precision CNNs.

Main Methods:

• Integration of vector dot products to unify convolution and fully connected layers, using row vectors of feature maps as the processing unit.
• Development of an accurate Design Space Exploration (DSE) model for optimizing design points per CNN layer.
• Implementation of dynamic partial reconfiguration to maximize resource access for each layer.

Main Results:

• Achieved average convolutional layer throughput of 28.985 GOP/s and 246.711 GOP/s for full precision on 7A100T and ZU15EG platforms, respectively.
• Demonstrated significant power efficiency improvements, with maximum gains of 23.989x and 15.376x over state-of-the-art FPGA implementations.
• Validated the approach through successful implementation of AlexNet and VGG16.

Conclusions:

• The proposed unified accelerator design effectively balances latency and resource consumption while eliminating data rearrangement overhead.
• The DSE model and dynamic partial reconfiguration enable optimized performance and resource utilization for diverse CNN architectures.
• This work presents a significant advancement in power-efficient, high-performance CNN acceleration on FPGAs.