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Related Experiment Video

Updated: May 2, 2026

High Throughput Microfluidic Rapid and Low Cost Prototyping Packaging Methods

High Throughput Microfluidic Rapid and Low Cost Prototyping Packaging Methods

Published on: December 23, 2013

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC.

Xiaoyong Song^1,2, Rui Lu^1,2, Zhichuan Guo^1,2,3

¹National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, China.

|April 27, 2024

Summary

This summary is machine-generated.

This study introduces a flexible, high-performance reconfigurable pipeline for FPGA-based SmartNICs. The design enables dynamic reconfiguration of network functions at runtime, achieving 100 Gbps throughput with low latency.

Keywords:

SmartNIC field programmable gate arrays (FPGA)pipeline reconfigurable match-action table switch

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Last Updated: May 2, 2026

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Area of Science:

Computer Engineering
Network Hardware

Background:

Current FPGA-based SmartNIC packet processing pipelines lack flexibility.
Commercial reconfigurable device designs are often closed-source, hindering customization.

Purpose of the Study:

To propose a high-performance, fully reconfigurable pipeline design for FPGA-based SmartNICs.
To enable dynamic reconfiguration of network functions without hardware modification or recompilation.

Main Methods:

Developed fully reconfigurable match-action units.
Implemented dynamic reconfiguration of match key fields and table sizes.
Designed a runtime configuration module for processing rules and action instructions.
Utilized Xilinx Alveo U200 board with Virtex UltraScale+ FPGA for implementation.

Main Results:

The designed pipeline supports fast reconfiguration for implementing new network functions.
Achieved a throughput of 100 Gbps.
Demonstrated low latency in packet processing.

Conclusions:

The proposed design offers a flexible and high-performance solution for FPGA-based SmartNIC packet processing.
Enables dynamic network function implementation, overcoming limitations of current inflexible and closed-source designs.