A Power-and-Area-Efficient Channel-Interleaved Neural Signal Processor for Wireless Brain-Computer Interfaces With...

Area of Science:

• Neuroscience
• Electrical Engineering
• Biomedical Engineering

Background:

• Wireless brain-computer interfaces (BCIs) require efficient neural signal processors (NSPs) to manage power and bandwidth constraints.
• Spike detection and clustering are crucial for extracting neurological information in neuroscience and clinical settings.

Purpose of the Study:

• To evaluate computational-friendly algorithms for spike detection and feature extraction.
• To design and implement a low-power, high-performance NSP ASIC for wireless BCIs.

Main Methods:

• Systematic evaluation of nonlinear energy operator (NEO) and first-and-second-derivative (FSDE) for spike detection.
• Application of 'perturbed' K-mean clustering for unsupervised spike classification.
• Implementation of a channel-interleaved NSP ASIC with a folding ratio of 16 in 65-nm CMOS technology.

Main Results:

• NEO and FSDE combined with 'perturbed' K-mean clustering demonstrated highest accuracy.
• The NSP ASIC achieved minimal power-and-area product, consuming 2-µW per channel.
• Attained 92% unsupervised spike classification accuracy and 98.3% data-rate reduction.

Conclusions:

• The developed NSP is highly promising for realizing high-channel-count wireless BCIs.
• The system effectively balances computational efficiency, accuracy, and resource constraints.
• This work paves the way for more sophisticated and practical BCI devices.