Highly-integrable analogue reservoir circuits based on a simple cycle architecture.

Area of Science:

• Physical reservoir computing
• Artificial intelligence hardware acceleration
• Analogue circuit design

Background:

• Physical reservoir computing leverages nonlinear physical systems for AI computation.
• Demand for highly integrable physical reservoirs is increasing, especially for edge AI.
• Challenges remain in achieving practical physical reservoirs with both high performance and integrability.

Purpose of the Study:

• To present a novel analogue circuit reservoir with a simple cycle architecture.
• To demonstrate its suitability for complementary metal-oxide-semiconductor (CMOS) chip integration.
• To evaluate its performance for practical AI applications.

Main Methods:

• Designed and implemented an analogue circuit reservoir with a cycle architecture.
• Utilized both hardware prototypes and simulations for evaluation.
• Conducted benchmarks using synthetic and real-world datasets.

Main Results:

• The developed analogue circuit reservoir achieved high prediction performance.
• Demonstrated sufficient memory capacity for practical applications.
• Showcased compatibility with CMOS chip integration.

Conclusions:

• The proposed analogue circuit reservoir offers a promising solution for high-performance, integrable AI accelerators.
• This approach addresses the demand for efficient edge AI computing hardware.
• Further applications in integrated AI acceleration are anticipated.