CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

Henry H Radamson1, Yuanhao Miao1, Ziwei Zhou1

  • 1Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China.

Summary

Moore's Law is ending, driving innovation in 3D transistors like gate-all-around (GAA) and fully depleted silicon-on-insulator (FDSOI) designs. These advanced transistor architectures aim to overcome scaling limits and enable future low-power electronics.

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