Related Experiment Video
Updated: Jun 25, 2025

Probing C84-embedded Si Substrate Using Scanning Probe Microscopy and Molecular Dynamics
Published on: September 28, 2016
Research on Single-Event Burnout Reinforcement Structure of SiC MOSFET
1Key Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University, Xi'an 710071, China.
This study enhances the single-event burnout (SEB) resistance of 1200 V Silicon Carbide (SiC) MOSFETs using structural reinforcements. Combining P+ body contact area expansion and a buffer layer significantly boosts SEB threshold voltage by 33%.
Area of Science:
- Semiconductor device physics
- Power electronics
- Radiation effects in electronics
Background:
- 1200 V Silicon Carbide (SiC) MOSFETs are crucial for high-power applications.
- Single-event burnout (SEB) poses a reliability risk due to heavy ion strikes.
- Existing SiC MOSFET designs require improved SEB resistance for harsh environments.
Purpose of the Study:
- To investigate SEB mechanisms in a novel 1200 V SiC MOSFET with split gate and embedded Schottky barrier diode (SBD).
- To develop and evaluate structural reinforcement techniques to enhance SEB resistance.
- To analyze the trade-offs between SEB improvement and device performance.
Main Methods:
- Device simulation using Sentaurus TCAD to model the SG-SBD-MOSFET structure.
- Analysis of single-event effect (SEE) transient currents and electric field distribution under heavy ion irradiation.
- Design and separate/combined evaluation of P+ body contact area expansion and multi-layer N-type interval buffer layer reinforcements.
Main Results:
- SEB threshold voltage increased by 16% with P+ body contact extension alone.
- SEB threshold voltage increased by 29% with the multi-layer N-type interval buffer layer alone.
- Combined reinforcement increased SEB threshold voltage by 33%, with a minor breakdown voltage reduction from 1632.935 V to 1403.135 V.
Conclusions:
- The proposed reinforcement structures effectively enhance SEB resistance in 1200 V SiC MOSFETs.
- The combined approach offers the most significant improvement in SEB threshold voltage.
- The reinforced devices maintain acceptable performance with a reduced voltage margin.
More Related Videos
08:02Rendering SiO2/Si Surfaces Omniphobic by Carving Gas-Entrapping Microtextures Comprising Reentrant and Doubly Reentrant Cavities or Pillars
Published on: February 11, 2020
06:57Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon
Published on: July 17, 2020
Related Concept Videos
Characteristics of MOSFET
Various vital parameters influence their functionality, which is crucial for theory and electronics applications. First, channel dimensions, precisely length, and width, are pivotal. The size of these channels affects the transistor's ability to carry current and switching speeds; shorter channels typically enable...
MOSFET: Enhancement Mode
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
MOSFET
In an n-MOSFET, the structure includes n-type source and drain...
MOSFET: Depletion Mode
The primary characteristic of depletion-mode MOSFETs is their ability to conduct current between the drain and source terminals without gate bias. This inherent conductivity...
MOS Capacitor
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
MOSFET Amplifiers