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Updated: Jun 25, 2025

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities
Published on: July 24, 2015
Study of graphene p-n junctions formed by the electrostatic modification of the SiO2 substrate
Tharanga R Nanayakkara1,2, U Kushan Wijewardena1,3, Annika Kriisa1
1Georgia State University, Atlanta, GA, 30303, USA.
Abstract:
We study the transport properties of mm-scale CVD graphene p-n junctions, which are formed in a single gated graphene field effect transistor configuration. Here, an electrical-stressing-voltage technique served to modify the electrostatic potential in the SiO2/Si substrate and create the p-n junction. We examine the transport characteristics about the Dirac points that are localized in the perturbed and unperturbed regions in the graphene channel and note the quantitative differences in the Hall effect between the perturbed and unperturbed regions. The results also show that the longitudinal resistance is highly sensitive to the external magnetic field when the Hall bar device operates as a p-n junction.
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