Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Ferroelectric transistors based on hafnia-based ferroelectrics exhibit tremendous potential as next-generation memories owing to their high-speed operation and low power consumption. Nevertheless, these transistors face limitations in terms of memory window, which directly affects their ability to support multilevel characteristics in memory devices. Furthermore, the absence of an efficient operational technique capable of achieving multilevel characteristics has hindered their development. To address these challenges, we present a gate stack engineering method and an efficient operational approach for ferroelectric transistors to achieve 16-level data per cell operation. By using the suggested engineering method, we demonstrate the attainment of a substantial memory window of 10 V without increasing the device area. Additionally, we propose a displacement current control method, facilitating one-shot programming to the desired state. Remarkably, we suggest the compatibility of these proposed methods with three-dimensional (3D) structures. This study underscores the potential of ferroelectric transistors for next-generation 3D memory applications.