Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact...

Area of Science:

• Semiconductor device physics
• Advanced transistor technology
• Nanoscale fabrication

Background:

• Vertical gate-all-around (V-GAA) transistors are crucial for future semiconductor technology but face fabrication challenges.
• Existing methods for fabricating V-GAA devices often involve complex processes like lift-off, impacting yield and performance.

Purpose of the Study:

• To introduce a novel dual-input logic gate circuit using 3D vertical transistors.
• To demonstrate a lift-off-free fabrication technique for nanoscale sub-20-nm V-GAA devices.
• To explore new design possibilities in advanced 3D logic circuitry.

Main Methods:

• Development of a novel contact and metallic line patterning technique without a conventional lift-off process.
• Implementation of a two-step oxidation process for field oxide and gate oxide formation on nanowires (NWs).
• Fabrication of V-GAA-NW transistors using the lift-off-free approach.

Main Results:

• V-GAA-NW transistors fabricated with the lift-off-free method show improved yield and reduced access resistance.
• Enhanced drive current and maintained immunity against short-channel effects were observed.
• Successful demonstration of elementary two-input logic gates within a single cell using VNW transistors.

Conclusions:

• The novel lift-off-free fabrication technique is effective for V-GAA-NW transistors.
• The developed approach offers improved device performance and fabrication efficiency.
• This work presents new possibilities for advanced logic circuitry design and routing in 3D integrated systems.