SHA-256 Hardware Proposal for IoT Devices in the Blockchain Context.

Area of Science:

• Computer Engineering
• Cryptography
• Embedded Systems

Background:

• Internet of Things (IoT) devices face security and privacy challenges.
• The SHA-256 algorithm is crucial for blockchain security but can be power-intensive.
• Existing SHA-256 implementations may not meet the performance and power demands of IoT.

Purpose of the Study:

• To implement SHA-256 on a Field-Programmable Gate Array (FPGA) for enhanced IoT security.
• To improve processing capacity and power efficiency in IoT devices using blockchain technology.
• To introduce a novel parallel clustered core architecture for SHA-256.

Main Methods:

• Developed a SHA-256 algorithm implementation utilizing clustered cores for parallel execution.
• Integrated the implementation onto a Xilinx Virtex 6 FPGA (xc6vlx240t-1ff1156).
• Analyzed FPGA resource utilization and performance metrics.

Main Results:

• Achieved a throughput of approximately 1.4 Gbps with 16 parallel SHA-256 cores.
• Demonstrated a significant dynamic power saving, nearly 1000 times less than previous works.
• Successfully validated the implementation on the specified FPGA.

Conclusions:

• The proposed FPGA-based SHA-256 implementation offers a viable solution for enhancing security and privacy in IoT devices.
• The parallel clustered core architecture significantly boosts processing capacity and power efficiency.
• This approach is well-suited for practical applications in blockchain-enabled IoT environments.