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    This study introduces a novel fully pipelined hardware accelerator for convolutional neural networks (CNNs). This pixel-by-pixel design significantly boosts processing speed and throughput for computer vision tasks, overcoming limitations of existing single or multi-computing engine architectures.

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    Area of Science:

    • Computer Engineering
    • Artificial Intelligence
    • Hardware Acceleration

    Background:

    • Current convolutional neural network (CNN) hardware accelerators, based on single or multi-computing engine (CE) architectures, face limitations in resource utilization and data throughput.
    • Existing accelerators struggle with large feature maps, often achieving speeds as low as 10 frames/s, which is insufficient for demanding applications like autonomous driving and radar detection.

    Purpose of the Study:

    • To address the performance bottlenecks of existing CNN hardware accelerators.
    • To propose a novel, fully pipelined hardware accelerator design optimized for pixel-level processing.
    • To enhance resource utilization and data throughput for CNNs, enabling high-speed AI applications.

    Main Methods:

    • Introduced a pixel-by-pixel processing strategy, minimizing the significance of traditional layer-based computation.
    • Developed a fully pipelined system by expanding each neural network layer into hardware, eliminating inter-layer buffers.
    • Maximized complete connectivity across the entire network by optimizing the generation of each output feature map (Ofmap) pixel.

    Main Results:

    • Achieved a processing speed of 4205.50 frames/s and a throughput of 4787.15 GOP/s at 211 MHz for a MobileNetV1 accelerator.
    • Demonstrated an output latency of 0.60 ms per image, significantly reducing processing time.
    • Confirmed the accelerator's universality across various CNN models, including MobileNetV1, MobileNetV2, and FashionNet.

    Conclusions:

    • The proposed fully pipelined, pixel-based hardware accelerator design offers substantial performance improvements over existing architectures.
    • This approach effectively overcomes limitations in resource utilization and data throughput, enabling CNNs for high-speed applications.
    • The universal design is suitable for diverse computer vision tasks, paving the way for advanced AI deployment in real-time scenarios.