Robust Quantum Gates against Correlated Noise in Integrated Quantum Chips

Area of Science:

• Quantum Computing
• Superconducting Circuits
• Quantum Error Correction

Background:

• Quantum circuits face new error sources as complexity increases.
• Standard gate fidelity metrics fail to predict performance in realistic, noisy environments.
• Robustness against prevalent error models is essential for scalable quantum technology.

Purpose of the Study:

• To experimentally realize robust quantum gates in superconducting circuits.
• To develop a geometric framework for diagnosing and correcting gate errors.
• To enhance the resilience of quantum gates against various noise types.

Main Methods:

• Utilized a geometric framework for error diagnosis and correction.
• Employed quantum process tomography and randomized benchmarking techniques.
• Tested gate robustness against quasistatic and spatially correlated noise.

Main Results:

• Demonstrated robust single-qubit gates against common coherent error sources.
• Successfully applied the method to nonstatic noise and two-qubit gates.
• Showcased resilience against a broad range of noise strengths.

Conclusions:

• The developed geometric framework provides a versatile toolbox for noise-resilient quantum circuits.
• This approach is crucial for improving the performance of complex superconducting quantum systems.
• Enables more reliable quantum computation in the presence of realistic noise.