Spatially Resolved Dielectric Loss at the Si/SiO_{2} Interface

Area of Science:

• Solid State Physics
• Materials Science
• Nanotechnology

Background:

• The silicon/silicon dioxide (Si/SiO2) interface contains trap states affecting electronic properties.
• These traps are critical for developing quantum sensors, computers, and nanoelectronic devices.

Purpose of the Study:

• To investigate the electric susceptibility of the Si/SiO2 interface with nanometer spatial resolution.
• To understand charge organization dynamics and dielectric loss mechanisms at this interface.

Main Methods:

• Utilized frequency-modulated atomic force microscopy (FM-AFM) for high-resolution measurements.
• Studied a patterned dopant delta layer buried near the Si/SiO2 interface.

Main Results:

• Determined charge organization timescales at the Si/SiO2 interface to be between 1-150 nanoseconds (ns).
• Observed significant increases in timescales around interfacial traps.
• Revealed highly spatially heterogeneous dielectric loss over nanometer length scales.

Conclusions:

• Dielectric loss in metal-insulator-semiconductor capacitor devices exhibits MHz to sub-MHz frequencies under time-varying gate biases.
• Interfacial traps play a key role in the observed charge dynamics and dielectric loss heterogeneity.