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Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

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Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model.

Jae Gwang Lim^1,2, Sung-Jae Park^1,3, Sang Min Lee^1,3

¹Center for Semiconductor Technology, Korea Institute of Science and Technology, Seoul, 02792, South Korea.

Scientific Reports

|August 2, 2024

Summary

This study presents a novel CMOS-memristor hybrid synapse circuit capable of emulating diverse spike-timing-dependent plasticity (STDP) rules for energy-efficient neuromorphic computing. The circuit successfully demonstrated associative learning, paving the way for scalable brain-inspired AI.

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Area of Science:

Neuromorphic Engineering
Artificial Intelligence
Materials Science

Background:

Neuromorphic computing aims for energy-efficient big data processing, with spiking neural networks (SNNs) and bio-plausible learning rules being key approaches.
Existing SNN hardware often implements standard spike-timing-dependent plasticity (STDP), but rarely captures the diverse STDP rules observed in the biological brain.

Purpose of the Study:

To propose and design a CMOS-memristor hybrid synapse circuit for hardware implementation of a Ca ion-based plasticity model.
To emulate various STDP curves using this hybrid circuit, moving beyond standard STDP implementations.
To demonstrate the circuit's capability in neural network operations, specifically associative learning.

Main Methods:

Developed a CMOS-memristor hybrid synapse circuit utilizing memristors for analog non-volatile memory.
Designed the circuit in four sub-blocks, leveraging memristor properties for plasticity emulation.
Employed an H-bridge circuit structure and PWM modulation for weight variation.
Implemented a Ca ion-based plasticity model to achieve diverse STDP curves.

Main Results:

Successfully emulated various STDP curves within a single CMOS-memristor hybrid circuit.
Demonstrated a simple neural network operation for associative learning (Pavlovian conditioning).
The memristor's non-volatile and analog properties were exploited for efficient synaptic weight updates.

Conclusions:

The proposed CMOS-memristor hybrid synapse circuit effectively emulates diverse STDP rules, addressing a gap in current SNN hardware.
This circuit facilitates the development of more biologically realistic neuromorphic systems.
The design shows promise for scalable neuromorphic computing applications through its potential for large-scale integration.