On the grain boundary charge transport in p-type polycrystalline nanoribbon transistors

Grain boundaries (GB) profoundly influence charge transport, and their localized potential barrier with a high density of defect states plays a crucial role in polycrystalline materials. There are a couple of models to estimate the density of states (DoS) of nanostructured materials in field-effect transistors (FETs) that probe interface traps between the semiconductor and dielectric but not at the grain boundaries. Here, we report on utilizing Levinson's and Seto's models of grain boundary transport and correlate them with the temperature-dependent hopping transport in copper iodide (CuI) polycrystalline nanoribbon (PNR) FETs. Experimentally, PNRs are obtained by e-beam lithography and thermal evaporation of CuI. To investigate the impact of GB, the devices are fabricated with different channel aspect ratios by varying widths (80, 260, and 570 nm) and lengths (20 to 90 μm). Owing to the high hole concentration, PNR FETs operate in depletion mode at 300 K. At various low temperatures (80-300 K), the figures-of-merits of FETs are estimated to understand device performance. We determine GB barrier heights, activation energy, and density of GB trap states and find equivalence between the two models. Furthermore, we calculate temperature-dependent hopping and trap-limited transport parameters to obtain DoS at the Fermi energy, trapped and free charge carrier density, localization length, hopping distance, hopping energy, etc. at various channel lengths. Based on this quantitative analysis, we propose a channel length-dependent GB barrier height variation due to the in-plane electric field and elucidate CuI energy band levels.