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Contact Resistance Engineering in WS2-Based FET with MoS2 Under-Contact Interlayer: A Statistical Approach.
Małgorzata Giza1, Michał Świniarski1, Arkadiusz P Gertych1
1Faculty of Physics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland.
ACS Applied Materials & Interfaces
|August 26, 2024
Summary
Researchers developed a new method to reduce contact resistance in 2D material devices. By inserting a molybdenum disulfide (MoS2) interlayer, they achieved over 60% lower resistance and a tenfold increase in performance for tungsten disulfide (WS2) field-effect transistors (FETs).
Area of Science:
- Materials Science
- Nanotechnology
- Electrical Engineering
Background:
- Fabrication of 2D material-based devices is hindered by challenges in achieving low-resistance electrical contacts.
- Standard metal deposition methods often result in Fermi level pinning (FLP), limiting control over Schottky barrier height at metal/2D material interfaces.
Purpose of the Study:
- To harness the Fermi level pinning (FLP) effect to reduce contact resistance in field-effect transistors (FETs).
- To introduce an under-contact interlayer strategy using 2D materials to improve device performance.
Main Methods:
- Developed a gold-assisted transfer method for fabricating complex heterostructures of transition metal dichalcogenide (TMD) monolayers with nanoscale precision.
- Utilized e-beam lithography for prepatterning TMD monolayers with lateral dimensions down to 100 nm.
- Fabricated tungsten disulfide (WS2) monolayer FETs with a molybdenum disulfide (MoS2) interlayer strategically placed at the metal contact interface (Au/MoS2/WS2 junction).
Main Results:
- Demonstrated a reduction in contact resistance exceeding 60% in WS2 FETs incorporating an MoS2 under-contact interlayer.
- Achieved a tenfold improvement in the on/off current ratio (Ion/Ioff) compared to devices without the interlayer.
- Observed enhanced device operation attributed to favorable band alignment at the Au/MoS2/WS2 heterostructure interface due to FLP.
- Systematically analyzed 160 devices, confirming consistent performance improvements and the impact of contact resistance.
Conclusions:
- The proposed under-contact interlayer approach effectively leverages FLP to significantly lower contact resistance in 2D material FETs.
- This method offers a viable strategy for fabricating high-performance 2D material-based electronic devices with improved contact properties.
- The findings highlight the importance of interface engineering for optimizing the electrical characteristics of nanoscale electronic components.
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