Reliability Simulation Analysis of TSV Structure in Silicon Interposer under Temperature Cycling

Area of Science:

• Materials Science
• Mechanical Engineering
• Electrical Engineering

Background:

• Semiconductor integration demands smaller chip sizes and advanced packaging like Through Silicon Via (TSV) technology.
• Increasing TSV aspect ratios and decreasing diameters introduce thermo-mechanical reliability concerns, especially in interposer substrates due to material mismatch.
• Electroplating defects in TSV copper pillars are common and can influence reliability.

Purpose of the Study:

• To conduct a thermo-mechanical analysis of TSV structures within complex interposer substrates.
• To investigate the thermal stress behavior and reliability of TSVs under variable temperature conditions (-55 °C to 85 °C).
• To evaluate the impact of electroplating defects on TSV reliability.

Main Methods:

• Developed an overall finite element model to identify critical TSV locations.
• Employed sub-model analysis to examine stress and deformation in the most critical TSV.
• Calculated the temperature cycle life based on stress and deformation analysis.

Main Results:

• The central TSV was identified as the most critical, exhibiting the highest equivalent stress.
• Maximum deformation showed periodic variations, while maximum equivalent stress accumulated over cycles, peaking at the TSV/RDL interface.
• The estimated temperature cycle life for the critical point is 3.1708 × 10^5 cycles.
• Electroplating defect 'b' was found to alleviate thermal stress in TSVs during temperature cycling.

Conclusions:

• Thermo-mechanical stress in TSVs is critical for advanced semiconductor packaging reliability.
• The location and presence of defects significantly influence TSV performance and lifespan.
• Findings are crucial for optimizing the design and manufacturing of high-reliability semiconductor packages.