Enhanced CPU Design for SDN Controller.

Area of Science:

• Computer Engineering
• Electrical Engineering
• Network Engineering

Background:

• Software-Defined Networking (SDN) centralizes network control for enhanced programmability.
• Traditional binary circuits face limitations in chip area, propagation delay, and energy consumption.
• Multiple-Valued Logic (MVL) and Carbon Nanotube Field-Effect Transistors (CNTFETs) offer potential improvements.

Purpose of the Study:

• To enhance SDN controller performance by optimizing the Central Processing Unit (CPU) using ternary logic.
• To introduce a novel 1-trit Ternary Full Adder (TFA) design based on CNTFET technology.
• To evaluate the proposed TFA's effectiveness in reducing propagation delay and Power-Delay Product (PDP).

Main Methods:

• Implementation of a new 1-trit Ternary Full Adder (TFA) using Carbon Nanotube Field-Effect Transistors (CNTFETs).
• Simulation and comparison of the proposed TFA against 17 existing designs (including binary and other ternary designs) using HSPICE.
• Evaluation of CPU utilization and performance metrics like propagation delay and Power-Delay Product (PDP).

Main Results:

• The proposed ternary TFA design demonstrates significant reductions in propagation delay.
• Reductions in propagation delay exceeded 99% compared to 2-bit binary FA CMOS-based designs.
• Over 78% reduction compared to 2-bit binary FA FinFET-based designs and substantial improvements over existing TFAs were achieved.

Conclusions:

• The novel ternary TFA design integrated into an SDN controller's CPU offers superior performance.
• This approach enhances CPU utilization and network programmability in SDN environments.
• The study highlights the potential of MVL circuits and CNTFETs for next-generation network infrastructure.