Ultrathin Small Outline Package Key Techniques for High-Speed Chips with Multi-Leads

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Manufacturing

Background:

• Developing advanced packaging solutions is crucial for high-speed semiconductor devices.
• Existing ultrathin small outline package (TSOP) technologies face limitations with large-sized, high-speed chips.
• Need for improved techniques in precise positioning, lead frame design, and assembly processes.

Purpose of the Study:

• To design and develop key technologies for ultrathin small outline packages (TSOP) for large-sized high-speed chips.
• To address technological challenges in chip packaging, including thickness reduction and sealing.
• To enhance the performance and manufacturability of advanced semiconductor packages.

Main Methods:

• Development of a 25 µm precise positioning dice attaching technique.
• Implementation of a lead frame unit structure without a base island.
• Introduction of a lead co-plane layout within the frame.
• Optimization of TSO package outline, frame unit arrangement, and frame distribution.

Main Results:

• Successful resolution of technological problems in thickness reduction, wafer cutting, chip bonding, and plastic sealing.
• Designed large-sized TSOP products exhibit high availability and reliability.
• Achieved low cost and a short production cycle for the developed packaging technique.

Conclusions:

• The developed TSOP technologies effectively address the challenges of packaging large-sized, high-speed chips.
• The new packaging solutions offer significant advantages in cost, reliability, and production efficiency.
• This advanced packaging technique is suitable for widespread application in intelligent electronic devices.