NEXUS: A 28nm 3.3pJ/SOP 16-Core Spiking Neural Network With a Diamond Topology for Real-Time Data Processing
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View abstract on PubMed
Summary
This summary is machine-generated.This study introduces NEXUS, a 16-core spiking neural network (SNN) chip that overcomes power and density limitations for brain-scale AI. Its novel network-on-chip (NoC) architecture ensures efficient, data-loss-free communication for advanced neuromorphic computing.
Area Of Science
- Neuromorphic Engineering
- Integrated Circuit Design
- Artificial Intelligence
Background
- Brain-scale Spiking Neural Networks (SNNs) face power and integration density challenges.
- Existing multi-core SNNs use Network-on-Chip (NoC) for efficiency but suffer information loss under high traffic.
- This necessitates novel architectures for reliable and efficient neuromorphic hardware.
Purpose Of The Study
- To present NEXUS, a 16-core SNN chip with a novel diamond-shaped NoC topology.
- To demonstrate a scalable NoC architecture that prevents data loss and minimizes latency.
- To showcase a compact router design and a neurosynaptic core enabling speed enhancements.
Main Methods
- Fabrication of a 16-core SNN chip using 28-nm CMOS technology, integrating 4096 Leaky Integrate-and-Fire (LIF) neurons and 1M synaptic weights.
- Implementation of a diamond-shaped NoC topology with a novel congestion management method eliminating FIFOs.
- Mapping of neural network models (MNIST classification, audio recognition) onto the fabricated chip.
Main Results
- The NEXUS chip achieves high performance with a peak throughput of 4.7 GSOP/s and low energy consumption (3.3 pJ/SOP).
- The NoC ensures no data loss with a maximum latency of 5.1 μs and features a compact router footprint (0.001 mm²).
- Demonstrated 92.3% accuracy for MNIST classification (8.4K-classification/s) and 87.4% for audio recognition.
Conclusions
- NEXUS offers a scalable and energy-efficient solution for brain-scale SNNs, addressing key limitations of current neuromorphic hardware.
- The proposed NoC architecture and congestion management are critical for reliable data transfer in high-traffic SNNs.
- The chip's performance in classification and recognition tasks validates its potential for real-world AI applications.
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