Impact of Program-Erase Operation Intervals at Different Temperatures on 3D Charge-Trapping Triple-Level-Cell NAND...

Area of Science:

• Solid-state physics
• Electrical engineering
• Materials science

Background:

• Three-dimensional charge-trapping (3D CT) NAND flash memory offers high capacity and low cost.
• Memory reliability is critical for multi-level-cell (MLC) technologies like triple-level-cell (TLC) and quad-level-cell (QLC).
• The intervals between program (P) and erase (E) operations significantly impact NAND flash memory reliability.

Purpose of the Study:

• To systematically investigate the impact of P/E cycle intervals on 3D CT TLC NAND flash memory reliability.
• To analyze the effects of different temperatures and P/E cycle counts on memory performance.
• To provide insights for optimizing NAND flash memory system lifetime.

Main Methods:

• Characterization of P/E cycling intervals under varying temperatures and cycle counts.
• Analysis of program disturb (PD), read disturb (RD), and data retention (DR).
• Comparison of fail bit counts (FBCs) at high temperature (HT) versus room temperature (RT).

Main Results:

• Fail bit counts during HT PD are lower than RT PD.
• Upshift error dominates HT PD, while downshift error dominates RT PD.
• Different P/E intervals are recommended for 3D CT TLC NAND based on operating temperatures.

Conclusions:

• Memory reliability of 3D CT TLC NAND is sensitive to P/E intervals and operating temperatures.
• Adjusting P/E intervals can mitigate reliability issues like PD and improve data retention.
• The findings offer guidance for optimizing the operational lifespan of NAND flash memory systems.