A Mixed Approach for Clock Synchronization in Distributed Data Acquisition Systems.

Area of Science:

• * Embedded Systems Engineering
• * Networked Control Systems
• * Scientific Instrumentation

Background:

• * Accurate timing synchronization is critical for multi-device data acquisition.
• * Existing System on Chip (SoC) architectures require robust clock synchronization solutions.
• * Field Programmable Gate Arrays (FPGAs) offer a flexible platform for hardware-based timing solutions.

Purpose of the Study:

• * To propose a simple and effective clock synchronization method for SoC architectures.
• * To integrate a Field Programmable Gate Array (FPGA) with a Central Processing Unit (CPU) for precise timing.
• * To ensure accurate data acquisition in distributed systems for scientific experiments.

Main Methods:

• * Implemented a software-based network synchronization protocol (NTP/PTP).
• * Utilized an FPGA to generate a clock reference synchronized with the system clock.
• * Employed fractional clock division and a Proportional Integral (PI) controller to maintain clock accuracy and prevent drift.
• * Demonstrated a specific implementation on the RedPitaya platform generating a 1 MHz clock.

Main Results:

• * Achieved precise clock synchronization between the FPGA-generated clock and the NTP-synchronized system clock.
• * Successfully prevented clock drift through real-time software monitoring and adjustment of the FPGA clock frequency.
• * Validated the system's performance in a distributed data acquisition setup for fast transient recording.

Conclusions:

• * The proposed FPGA-based clock synchronization method is effective for SoC architectures.
• * This approach enhances the reliability of distributed data acquisition systems for high-precision scientific applications.
• * The system is suitable for demanding environments such as the ITER neutral beam test facility.