Streamline-directed tunable deterministic lateral displacement chip: A numerical approach to efficient particle
Ali Kheirkhah Barzoki1, Amir Shamloo2
1Department of Mechanical Engineering, Sharif University of Technology, Tehran, Iran.
Abstract:
In conventional Deterministic Lateral Displacement (DLD), the migration behavior of a particle of specific size is determined by the critical diameter (Dc), which is predefined by the device's geometry. In contrast to the typical approach that alters the angle between the pillar array and fluid streamlines by modifying the geometrical parameters, this study introduces a novel perspective that focuses on changing the direction of the streamlines. The proposed technique offers a tunable DLD chip featuring a straightforward design that allows for easy fabrication. This chip features one completely horizontal pillar array with two bypass channels on the top and bottom of the DLD chamber. The width of these bypass channels changes linearly from their inlet to their outlet. Two design configurations are suggested for this chip, characterized by either parallel or unparallel slopes of the bypass channels. This chip is capable of generating a wide range of Dc values by manipulating two distinct control parameters. The first control parameter involves adjusting the flow rates in the two bypass channels. The second control parameter entails controlling the slopes of these bypass channels. Both of these parameters influence the direction of particle-carrying streamlines resulting in a change in the path-line of the particles. By changing the angle of streamlines with pillar array, the Dc can be tuned. Prior to determining the Dc for each case, an initial estimation was made using a Python script that utilized the streamline coordinates. Subsequently, through FEM modeling of the particle trajectories, precise Dc values were ascertained and compared with the estimated values, revealing minimal disparities. By adjusting the flow rate and slope of the bypass channels, maximum Dc ranges of 4-10 μm and 8-13 μm can be achieved, respectively. This innovative chip enables the attainment of Dc values spanning from 0.5 to 14 μm.
