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A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
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Metal-oxide-semiconductor field-effect Transistors, or MOSFETs, play a critical role in electronic circuits. They are primarily utilized for amplifying and switching signals.
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The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) plays a pivotal role in modern electronics thanks to its versatility and efficiency in controlling electrical currents. This device, also known as IGFET, MISFET, and MOSFET, has three main terminals: the Source, Drain, and Gate. MOSFETs are classified into n-channel or p-channel types based on the doping characteristics of their substrate and the source or drain regions.
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Paving the Way for Pass Disturb-Free Vertical NAND Storage via a Dedicated and String-Compatible Pass Gate.

Zijian Zhao1, Sola Woo2, Khandker Akif Aabrar2

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This summary is machine-generated.

This study introduces a dual-port cell design for vertical NAND storage, eliminating pass disturbance. This innovation enhances reliability in high-density 3D NAND flash memory.

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Area of Science:

  • Electrical Engineering
  • Materials Science
  • Semiconductor Device Physics

Background:

  • Vertical NAND flash memory is crucial for high-density data storage.
  • Single-port cell designs in vertical NAND suffer from pass disturbance, limiting performance and reliability.
  • Pass disturbance arises from unintended signal leakage during read/write operations.

Purpose of the Study:

  • To propose and validate a novel dual-port cell design for vertical NAND storage.
  • To eliminate pass disturbance in vertical NAND flash memory.
  • To ensure compatibility with existing 3D NAND architectures and enable further scaling.

Main Methods:

  • Development of a dual-port cell architecture with a dedicated, string-compatible pass gate.
  • Theoretical analysis of electric field interactions (depolarization and screening effects) in high-threshold-voltage (HVT) and low-threshold-voltage (LVT) states.
  • Combined use of device simulations and experimental fabrications to verify the design's performance.
  • Integration strategy for the proposed design into scaled vertical NAND FeFET strings and 3D NAND.

Main Results:

  • The dual-port design effectively eliminates pass disturbance through unique field modulation in HVT and LVT states.
  • Simulations and experiments confirm disturb-free operation within a NAND string, a significant improvement over single-port designs.
  • The proposed pass gate can be integrated into existing 3D NAND with minimal overhead via a global bottom contact.

Conclusions:

  • The dual-port cell design offers a robust solution to the pass disturbance challenge in vertical NAND.
  • This design facilitates the development of more reliable and scalable high-density 3D NAND flash memory.
  • The proposed architecture is compatible with current manufacturing processes, paving the way for future advancements.