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Updated: Jun 10, 2025

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Low Contact Resistance WSe2 p-Type Transistors with Highly Stable, CMOS-Compatible Dopants
Inha Kim1,2, Naoki Higashitarumizu1,2,3, I K M Reaz Rahman1,2
1Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720, United States.
Abstract:
High contact resistance has been a bottleneck in developing high-performance transition-metal dichalcogenide (TMD) based p-type transistors. We report degenerately doped few-layer WSe2 transistors with contact resistance as low as 0.23 ± 0.07 kΩ·μm per contact by using platinum(IV) chloride (PtCl4) as the p-type dopant, which is composed of ions compatible with the complementary metal-oxide-semiconductor (CMOS) fabrication process. Top-gated devices with a gate length of 200 nm showed good switching behaviors, implying that the dopant diffusion into the gate stack is not significant. The devices showed nearly identical performance after being kept in air for 86 days without any encapsulation while retaining the degenerately doped states at 78 K with pressure lower than 10-5 Torr, highlighting the stability of the dopants. The presented method sets forth the availability of highly stable methods for pattern doping the transistors with a thinned Schottky barrier width for low contact resistance devices.
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