Parallel Lossless Compression of Raw Bayer Images on FPGA-Based High-Speed Camera

Area of Science:

• Digital image processing
• Hardware implementation
• Data compression

Background:

• Real-time lossless compression for high-speed, high-resolution cameras presents significant bandwidth and storage challenges.
• Existing methods may struggle with the demands of high-resolution imaging systems.

Purpose of the Study:

• To develop and implement a hardware-based lossless image compression algorithm suitable for FPGA cameras.
• To address the challenges of real-time data processing for high-speed imaging.

Main Methods:

• Hardware implementation of a Bayer color filter array lossless compression algorithm on an FPGA.
• Utilizing Golomb-Rice entropy coding and integer operators for efficient processing.
• Employing a tree-like pipeline structure for parallel processing of 16 pixels.

Main Results:

• Achieved up to 56% reduction in image size for high-resolution images.
• Pipelined implementation reached operating frequencies of 320 MHz.
• Parallel processing enabled data throughput of 40 Gbit/s with low memory usage.

Conclusions:

• The proposed algorithm offers an effective solution for real-time lossless image compression in high-speed camera systems.
• Hardware acceleration on FPGAs is crucial for meeting the performance demands of modern imaging.
• The parallelized, pipelined approach significantly enhances data throughput and reduces storage needs.