A Field-Programmable Gate Array-Based Adaptive Sleep Posture Analysis Accelerator for Real-Time Monitoring

Area of Science:

• Biomedical Engineering
• Computer Engineering
• Gerontology

Background:

• Real-time sleep posture monitoring is crucial for elderly and patient care.
• Existing methods face challenges in accuracy and real-time processing.
• Edge computation offers a promising solution for on-device, low-latency monitoring.

Purpose of the Study:

• To develop a hardware-based edge computation system for real-time sleep posture monitoring.
• To enhance patient care and support for the elderly through accurate posture detection.
• To implement and validate an FPGA-based algorithm for adaptive posture classification.

Main Methods:

• Utilized minimally optimized sensing modules and fusion techniques for initial posture detection.
• Employed posture-learning processing elements (PEs) for standard and adaptive posture evaluation.
• Developed a Field-Programmable Gate Array (FPGA)-based Hierarchical Binary Classifier (HBC) algorithm for real-time classification.
• Integrated Internet of Things (IoT) and display devices for seamless communication of posture data.

Main Results:

• Achieved real-time sleep posture detection and classification using the FPGA-based HBC algorithm.
• Demonstrated effective posture learning and analysis through customized VLSI architectures.
• Validated the system's performance using a Zed Board-based FPGA Xilinx board.

Conclusions:

• The proposed system effectively monitors sleep posture in real time for elderly and patient care.
• Hardware-based edge computation and FPGA implementation provide an efficient solution for posture monitoring.
• The system facilitates timely communication to attendant/support services, improving care outcomes.