A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

Area of Science:

• Digital circuit design
• VLSI technology
• Computer arithmetic

Background:

• Multipliers are critical for integrated circuits, impacting efficiency and performance.
• Vedic multipliers offer inherent speed and efficiency based on ancient Indian mathematics.
• Optimizing multiplier design is key for advanced computational tasks.

Purpose of the Study:

• To analyze and compare 4-bit Vedic multiplier designs using GDI, CMOS, and TG technologies.
• To evaluate performance, area, and power consumption across different adder architectures (RCA, CLA, CSA).
• To identify the most effective technology and adder combination for efficient multiplier implementation.

Main Methods:

• Designing and optimizing 4-bit Vedic multipliers in GDI, CMOS, and TG technologies.
• Integrating various adder architectures: Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA), and Carry Skip Adder (CSA).
• Evaluating designs using parameters like transistor count, delay, power dissipation, and power-delay product (PDP) in 32 nm technology via Tanner EDA.

Main Results:

• Gate Diffusion Input (GDI) technology showed significant advantages over CMOS and TG.
• GDI-based Vedic multipliers exhibited lower delay, reduced area, and decreased power consumption.
• The study quantified improvements in Power-Delay Product (PDP) favoring GDI implementations.

Conclusions:

• GDI technology presents a highly effective approach for designing efficient 4-bit Vedic multipliers.
• The choice of technology and adder architecture significantly impacts circuit performance metrics.
• This research provides valuable insights for optimizing digital signal processing and arithmetic circuit designs.