A Ku-Band Fully Differential Low-Power High-Input P1dB Low-Noise Amplifier.

Area of Science:

• Electrical Engineering
• Microwave Engineering
• Semiconductor Device Physics

Background:

• Low-noise amplifiers (LNAs) are critical components in radio frequency (RF) receiver systems, impacting overall system sensitivity and performance.
• Achieving high input linearity, low noise figure (NF), and low power consumption simultaneously in LNAs presents a significant design challenge.
• Fully differential architectures offer advantages in common-mode noise rejection and harmonic suppression, crucial for advanced RF applications.

Purpose of the Study:

• To design and implement a fully differential, low-power Ku-band low-noise amplifier (LNA).
• To enhance the input 1 dB compression point (P1dB) and improve common-mode noise rejection and second harmonic cancellation.
• To optimize the LNA for a balance of power consumption, noise figure, and linearity.

Main Methods:

• Employed a two-stage fully differential common-source (CS) topology.
• Utilized large transistors in the first stage for power and NF optimization.
• Incorporated class AB bias in the output stage for improved P1dB, power consumption, and linearity.
• Fabricated the LNA using 65 nm bulk complementary metal oxide semiconductor (CMOS) technology.

Main Results:

• Achieved a minimum noise figure (NF) of 2.7 dB at 13.6 GHz.
• Obtained a maximum gain of 19.92 dB at 12.2 GHz.
• Measured an input P1dB of -7.45 dBm and an output P1dB (OP1dB) of 10.09 dBm at 15.6 GHz.
• Demonstrated low power consumption of 11 mW at a 1 V supply.
• Achieved a compact core size of 0.75 mm × 0.35 mm.

Conclusions:

• The proposed fully differential LNA effectively enhances input P1dB, common-mode noise rejection, and linearity.
• The design achieves a competitive noise figure and gain with low power consumption, suitable for Ku-band applications.
• The 65 nm CMOS implementation demonstrates the feasibility of high-performance, compact LNAs for modern wireless systems.