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Floorplanning with I/O Assignment via Feasibility-Seeking and Superiorization Methods.

Shan Yu1, Yair Censor2, Guojie Luo3

  • 1Department of Information and Computational Sciences, School of Mathematical Sciences, Peking University, Beijing, China.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems : a Publication of the IEEE Circuits and Systems Society
|December 30, 2024
PubMed
Summary
This summary is machine-generated.

This study introduces a novel feasibility-seeking approach for complex floorplanning problems, improving efficiency and solution quality. The method enhances convergence and balances wirelength with runtime for better integrated circuit design.

Keywords:
Feasibility-seekingfloorplanning, I/O assignmentlocal convergencenon-convexprojection algorithmssuperiorization method

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Area of Science:

  • Computer Science
  • Electrical Engineering
  • Algorithm Design

Background:

  • Floorplanning problems involve complex, heterogeneous constraints that challenge conventional algorithms.
  • Existing projection-based feasibility-seeking methods lack guaranteed convergence and are sensitive to initialization.
  • Algorithmic divergence and oscillation are significant issues in current feasibility-seeking approaches.

Purpose of the Study:

  • To develop a robust and efficient feasibility-seeking framework for complex floorplanning problems.
  • To improve the convergence properties and initialization sensitivity of projection-based algorithms.
  • To integrate superiorization methods for bridging feasibility-seeking and constrained optimization in floorplanning.

Main Methods:

  • A quantitative property for optimal initial point selection was identified and analyzed.
  • A resetting strategy was implemented to mitigate algorithmic divergence in projection-based methods.
  • The superiorization method (SM) was applied to steer iterations towards feasible solutions with reduced wirelength.

Main Results:

  • The proposed Per-RMAP achieved legal floorplanning 166x faster than branch-and-bound (B&B) with a 5% wirelength increase.
  • Incorporating I/O assignment constraints yielded a 6% wirelength improvement.
  • For soft modules, a 15% runtime improvement was observed compared to the state-of-the-art analytical method PeF.

Conclusions:

  • The novel algorithmic flow effectively handles diverse floorplanning constraints, including I/O assignment and soft modules.
  • The approach demonstrates a significant improvement in runtime efficiency while maintaining competitive solution quality.
  • This work provides a balanced and adaptable solution for complex, real-world floorplanning challenges.