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Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

692
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
692

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Percolation theory-based KMC simulation for scaled Fe-FET based multi-bit computing-in-memory with temperature

Qingxiao Zhu1,2, Lihua Xu1,2, Zhidao Zhou1,2

  • 1State Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, People's Republic of China.

Nanotechnology
|January 2, 2025
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Summary
This summary is machine-generated.

This study explores how percolation transport affects ferroelectric field-effect transistor (FeFET) multi-value storage. Decreasing aspect ratio improves FeFET polarization, reducing device variations and enhancing state separation for reliable computing.

Keywords:
FeFETdevice-to-device variationmultilevel cell (MLC)percolation

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Area of Science:

  • Materials Science
  • Electrical Engineering
  • Computational Physics

Background:

  • Ferroelectric field-effect transistors (FeFETs) are promising for multi-value storage.
  • Percolation transport mechanisms significantly influence FeFET performance.
  • Device-to-device variations and state overlapping are critical challenges for multi-bit applications.

Purpose of the Study:

  • To investigate the impact of percolation transport on FeFET multi-value storage.
  • To analyze the influence of aspect ratio and temperature on FeFET characteristics.
  • To propose solutions for reliability issues in FeFET-based in-memory computing.

Main Methods:

  • Kinetic Monte-Carlo (KMC) simulations were employed to model percolation transport.
  • Aspect ratio and temperature dependencies were systematically studied.
  • High-temperature characterization was used to analyze amorphous channel disorder effects.

Main Results:

  • Decreasing device aspect ratio enhances ferroelectric polarization, mitigating variations and improving state separation.
  • Amorphous channel disorder, coupled with multi-domain dynamics, influences percolation transport.
  • KMC simulations predicted multi-value distributions from 300 K to 400 K.

Conclusions:

  • Percolation transport plays a crucial role in FeFET multi-value storage reliability.
  • Device design (aspect ratio) and material properties (channel disorder) impact performance.
  • An efficient write-verify scheme can mitigate state overlapping for improved multi-bit computing.