A Second-Order True-VCO ADC Employing a Digital Pseudo-DCO Suitable for Sensor Arrays

Area of Science:

• Mixed-signal integrated circuit design
• Analog-to-Digital Converters (ADCs)
• Sensor technology

Background:

• Traditional ADCs face challenges in power consumption and scalability for modern sensor applications.
• Voltage-Controlled Oscillators (VCOs) offer potential for high-resolution and low-power data conversion.

Purpose of the Study:

• To implement and validate a novel VCO-based ADC architecture.
• To demonstrate reduced power consumption and silicon footprint through a scalable digital-to-frequency converter.
• To explore dynamic performance adjustment for power-resolution trade-offs.

Main Methods:

• Designed and simulated a VCO-based ADC architecture in a 130 nm CMOS technology.
• Utilized a novel, scalable, and process, voltage, and temperature (PVT) invariant digital-to-frequency converter.
• Employed a pseudo-differential configuration for enhanced performance.

Main Results:

• Achieved an effective number of bits (ENOB) of 12 bits at a 1 MHz sampling rate within the audio bandwidth.
• Demonstrated low power consumption of 105.57 μW and a small silicon footprint of 0.034 mm².
• Validated dynamic adjustment of resolution and power consumption without altering the sampling rate.

Conclusions:

• The proposed VCO-based ADC offers a power-efficient and scalable solution for high-resolution data conversion.
• Its suitability for multiple instantiations on a System-on-Chip (SoC) makes it ideal for sensor array applications, including biomedical and spatial audio.
• The architecture provides flexibility for dynamic performance tuning, balancing power and resolution.