A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms.

Area of Science:

• Computer Engineering
• Hardware Acceleration
• Artificial Intelligence

Background:

• Multi-FPGA prototyping enables real-world testing and cycle-accurate design validation.
• Inter-FPGA routing is a critical and time-consuming step in multi-FPGA prototyping.
• The complexity of inter-FPGA routing increases with modern hardware designs.

Purpose of the Study:

• To develop and evaluate a Reinforcement Learning (RL)-based framework to expedite the inter-FPGA routing process.
• To optimize the RL framework's exploration-exploitation trade-off (ϵ-greedy approach) without compromising Quality of Results (QoR).

Main Methods:

• Integration of an RL-based framework for inter-FPGA routing.
• Implementation of an ϵ-greedy strategy within the RL framework.
• Comparative analysis against established routability-driven and timing-driven routing approaches using fourteen complex benchmarks.

Main Results:

• The proposed RL framework achieved an average speedup of 45% in inter-FPGA routing compared to routability-driven methods.
• The RL framework provided an average speedup of 32% compared to timing-driven routing approaches.
• Overall backend flow speedup of 22% and 15% was observed against routability- and timing-driven approaches, respectively.

Conclusions:

• The RL-based framework effectively accelerates inter-FPGA routing in multi-FPGA prototyping.
• This acceleration contributes to a significant overall speedup of the hardware design backend flow.
• The proposed method offers a promising solution for complex prototyping challenges.