Hardware-efficient preparation of architecture-specific graph states on near-term quantum computers

Area of Science:

• Quantum Computing
• Quantum Information Science

Background:

• Preparing highly entangled quantum states is crucial for quantum computing applications.
• Errors in current quantum hardware limit the fidelity and scale of these entangled states.
• Specialized compilation methods can improve entangled state preparation on near-term quantum computers.

Purpose of the Study:

• To develop an optimized compilation method for preparing architecture-specific graph states.
• To address the limitations of preparing highly entangled states on noisy quantum hardware.

Main Methods:

• Defined a formal model for discrete constraint optimization for quantum circuit compilation.
• Incorporated gate cancellations, commutations, and accurate gate timing into the optimization model.
• Quantified state quality using stabilizer measurements and fidelity calculations.

Main Results:

• Reduced error by 3.5x on average for a seven-qubit graph state compared to Qiskit.
• Reduced error by 6.4x on average for a linear eight-qubit graph state.
• Demonstrated improved fidelity and scalability for graph state preparation.

Conclusions:

• The developed compilation method enhances the fidelity and scale of entangled states.
• This approach offers a pathway to more robust quantum computing applications.
• The method effectively mitigates errors in gate-based quantum computing hardware.