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Area of Science:

  • Computer Engineering
  • Artificial Intelligence
  • Memory Technologies

Background:

  • In-memory computing offers reduced latency and power for AI accelerators.
  • Hardware variations in emerging memory technologies can degrade neural network accuracy.
  • Compromised accuracy poses risks in safety-critical AI applications.

Purpose of the Study:

  • To investigate technology-related sources of hardware variations in in-memory computing.
  • To propose an architectural mitigation strategy using checksum codes for error detection and correction.
  • To optimize the solution's overhead using hardware-software co-design techniques.

Main Methods:

  • Analysis of technology-related sources of hardware variations.
  • Implementation of a runtime error detection and correction strategy with two checksum codes.
  • Application of accuracy-aware hardware-software co-design for optimization.

Main Results:

  • The proposed solution effectively mitigates accuracy degradation across various AI algorithms and technologies.
  • Achieved >95% original accuracy recovery with <40% area and <30% latency overhead.
  • Outperforms state-of-the-art solutions and traditional redundancy techniques like triple modular redundancy.

Conclusions:

  • The developed mitigation strategy enhances the reliability of in-memory computing for AI accelerators.
  • Hardware-software co-design is crucial for efficient error mitigation in AI systems.
  • The approach offers a promising solution for secure and accurate AI in safety-critical applications.