Sparse Convolution FPGA Accelerator Based on Multi-Bank Hash Selection.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Deep convolutional neural network (DCNN) acceleration is crucial for AI, but general-purpose devices lack efficiency for sparse models.
• Existing neural network accelerators face challenges in optimal efficiency, low latency, and minimal power consumption.
• Sparse neural network acceleration is an active research area with potential for further optimization.

Purpose of the Study:

• To investigate and propose three key techniques for hardware acceleration of sparse neural networks.
• To enhance energy efficiency by designing specialized circuits that eliminate computations on zero values in sparse kernels.
• To improve off-chip memory access efficiency and reduce latency in convolutional neural network accelerators.

Main Methods:

• Developed a specialized computational circuit to detect and skip zero-value computations in sparse convolutional kernels.
• Utilized a Vitis HLS compiler optimization plugin to enhance on-chip bandwidth utilization for data access patterns.
• Proposed a shared feature map cache with a hash-based indexing algorithm for efficient asynchronous convolution, reducing on-chip memory usage.

Main Results:

• The specialized circuit enhanced energy efficiency by eliminating zero-value computations.
• Compiler optimizations improved off-chip memory access efficiency and data handling.
• The shared cache design enabled efficient asynchronous convolution, conserving on-chip resources.
• ResNet50 inference on an Intel Arria 10 1150GX FPGA achieved 497 GOPS throughput (1579 GOPS equivalent) at 22W power consumption.

Conclusions:

• The proposed techniques significantly improve the efficiency, latency, and power consumption of sparse neural network accelerators.
• The optimized accelerator demonstrates high performance and energy efficiency for DCNN inference tasks.
• This work provides a viable solution for deploying efficient neural network hardware acceleration.