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In electrical circuits, resistors can be connected in series, sequentially linked one after the other. In a series configuration, the same current flows through each resistor. Ohm's law is a fundamental principle to understand the behavior of resistors in series. It expresses the voltage across these resistors in terms of the current and resistance.
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Pass-Transistor-Enabled Split Input Voltage Level Shifter for Ultra-Low-Power Applications.

Chakali Chandrasekhar1, Mohammed Mahaboob Basha2, Sari Mohan Das3

  • 1Department of ECE, Sri Venkateswara College of Engineering, Tirupati 517507, AP, India.

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|January 25, 2025
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Summary

A new Pass-Transistor-Enabled Split Input Voltage Level Shifter (PVLS) offers energy efficiency and speed in integrated circuits. This low-power design achieves wide voltage conversion with minimal area and delay.

Keywords:
IoT applicationslow threshold voltagemulti-threshold CMOSpower-efficientsub-threshold operation

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Area of Science:

  • Integrated Circuit (IC) Design
  • Low-Power Electronics
  • Semiconductor Device Physics

Background:

  • Sub-threshold voltage management is crucial for energy efficiency and speed in modern integrated circuits (ICs).
  • Level shifters (LSs) are essential for signal integrity and reliable operation across multiple voltage domains in ICs.

Purpose of the Study:

  • To design a Pass-Transistor-Enabled Split Input Voltage Level Shifter (PVLS) for area, delay, and power-efficient applications.
  • To achieve a wide voltage conversion range with enhanced signal integrity and reliable operation.

Main Methods:

  • The proposed PVLS integrates a pull-up and pull-down network for level-up/down shifts.
  • Incorporation of multi-threshold CMOS technique and a load-balancing driving split inverter to minimize static current and leakage power.
  • Design implemented using 55 nm CMOS technology.

Main Results:

  • The PVLS demonstrates efficient low-power operation with dynamic power consumption of 2.00 nW.
  • Achieved a wide voltage conversion range from 0.3 V to 1.3 V.
  • Exhibits a minimal silicon area of 7.66 µm², a propagation delay of 90 ps at 1 MHz.

Conclusions:

  • The PVLS offers a significant advancement in low-power, high-performance level shifting for ICs.
  • The design provides an optimal solution for energy-efficient applications requiring wide voltage conversion.
  • The minimal area and low power consumption make it suitable for advanced integrated circuit designs.