LDPC-cat codes for low-overhead quantum computing in 2D.

Area of Science:

• Quantum Computing
• Quantum Error Correction
• Quantum Information Science

Background:

• Physical qubit errors are a major hurdle for large-scale quantum computing.
• Current error correction methods demand a substantial number of physical qubits, increasing overhead.
• Existing strategies like low-density parity check (LDPC) codes and cat qubits offer partial solutions.

Purpose of the Study:

• To develop a highly efficient quantum computing architecture with significantly reduced qubit overhead.
• To combine LDPC codes and cat qubits for synergistic error suppression.
• To enable the implementation of 100 logical qubits on a compact 758-qubit chip.

Main Methods:

• Integration of low-density parity check (LDPC) codes with cat qubits.
• Design of a 2D hardware architecture with short-range interactions and low-weight stabilizers.
• Implementation of fault-tolerant universal logical gates using an additional layer of routing cat qubits.

Main Results:

• Achieved an extremely low overhead architecture for quantum error correction.
• Demonstrated the implementation of 100 logical qubits on a 758-qubit chip with a physical error rate of ~0.1%.
• Attained a total logical error probability per cycle per logical qubit (ϵ_L) below 10^-8.
• Maintained local connectivity and high parallelization capacity for logical gates.

Conclusions:

• The proposed architecture offers a viable path towards scalable quantum computing by minimizing qubit overhead.
• The design is compatible with existing hardware constraints, similar to surface codes.
• The architecture supports efficient implementation of logical gates, enhancing practical quantum computation.