Novel three-dimensional stacked capacitorless DRAM architecture using partially etched nanosheets for high-density...

Area of Science:

• Semiconductor device physics
• Advanced memory technologies
• Materials science for electronics

Background:

• Traditional dynamic random access memory (DRAM) faces scaling limitations due to capacitor requirements.
• Capacitorless 1T-DRAM architectures offer potential for higher integration density.
• Nanosheet (NS) transistors present a promising avenue for advanced DRAM designs.

Purpose of the Study:

• To introduce and evaluate a novel three-dimensional stacked capacitorless 1T-DRAM architecture using partially etched nanosheets (PE NS).
• To investigate the performance benefits of the PE NS 1T-DRAM compared to conventional NS 1T-DRAM.
• To assess the device's potential for overcoming current DRAM scaling challenges.

Main Methods:

• Utilizing Sentaurus technology computer-aided design (TCAD) simulations for device modeling and analysis.
• Comparing the electrical characteristics of the proposed PE NS 1T-DRAM with a conventional NS 1T-DRAM.
• Evaluating key performance metrics including retention time (RT) and sensing margin (SM).

Main Results:

• The PE NS 1T-DRAM demonstrates significantly superior retention time and sensing margin compared to conventional NS 1T-DRAM.
• The proposed architecture meets and exceeds the International Roadmap for Devices and Systems (IRDS) memory criteria (RT > 64 ms at 358 K).
• The device exhibits robustness, maintaining over 89% of its SM and RT under various disturbance conditions.

Conclusions:

• The PE NS 1T-DRAM architecture effectively overcomes scaling limitations by leveraging the floating body effect and eliminating capacitors.
• The enhanced performance is attributed to the extension region acting as a potential well and suppressing Shockley-Read-Hall recombination.
• The PE NS 1T-DRAM design shows strong potential for enabling future high-density memory applications.