Low-power 2D gate-all-around logics via epitaxial monolithic 3D integration

Area of Science:

• Materials Science and Engineering
• Nanotechnology
• Semiconductor Physics

Background:

• Transistor miniaturization is crucial for advancing device performance, energy efficiency, and integration density.
• Two-dimensional (2D) semiconductors offer potential for gate-all-around (GAA) field-effect transistors (FETs) at angstrom nodes, promising superior gate control for power scaling.
• Scalable integration of 2D GAA heterostructures with atomically smooth interfaces remains a significant challenge.

Purpose of the Study:

• To develop a wafer-scale, monolithic 3D integrated 2D GAA heterostructure.
• To achieve atomically smooth interfaces between 2D semiconductors and high-κ dielectrics for improved transistor performance.
• To demonstrate the potential of 2D GAA FETs for beyond-silicon electronics.

Main Methods:

• Low-temperature monolithic three-dimensional integration.
• Epitaxial integration of high-mobility 2D semiconductor Bi₂O₂Se with a high-κ layered native-oxide dielectric Bi₂SeO₅.
• Fabrication of scaled 2D GAA FETs with 30 nm gate length.

Main Results:

• Achieved wafer-scale, multi-layer-stacked, single-crystalline 2D GAA configuration with atomically smooth interfaces.
• Demonstrated high electron mobility of 280 cm² V^-1 s^-1 and a near-ideal subthreshold swing of 62 mV dec^-1.
• Exhibited ultralow operation voltage (0.5 V), high on-state current (>1 mA μm^-1), ultralow intrinsic delay (1.9 ps), and excellent energy-delay product (1.84 × 10^-27 Js μm^-1).

Conclusions:

• The developed wafer-scale 2D GAA system offers significant performance and power advantages.
• This approach overcomes key integration challenges for 2D materials in advanced transistor architectures.
• The technology holds strong potential for future monolithic 3D integrated circuits beyond silicon.