GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling.

Area of Science:

• Explores probabilistic computing, a novel paradigm leveraging probabilistic bits (p-bits) for computational tasks.
• Focuses on the application of p-bits, realized via emerging devices like magnetic tunnel junctions, in complex problem-solving.

Background:

• Traditional CMOS logic faces limitations in handling complex computations like simulated annealing and machine learning.
• Probabilistic computing using p-bits offers an efficient alternative, but device variability in emerging hardware was presumed detrimental.

Purpose of the Study:

• To investigate the impact of device variability on the performance of probabilistic computing algorithms.
• To develop and present a GPU-accelerated, open-source simulated annealing framework for p-bit-based computations.

Main Methods:

• Developed a simulated annealing framework utilizing p-bits, incorporating key device variability factors: timing, intensity, and offset.
• Employed CUDA-based simulations to model real-world device behavior and assess computational performance.
• Evaluated the framework on the MAX-CUT benchmark for problem sizes ranging from 800 to 20,000 nodes.

Main Results:

• Demonstrated that device variability, contrary to expectations, can enhance algorithm performance, particularly through timing variability.
• Achieved a two-order magnitude speedup compared to CPU implementations using the GPU-accelerated framework.
• Successfully modeled critical device variability factors to accurately reflect practical hardware behavior.

Conclusions:

• Device variability in p-bit hardware is not solely a performance impediment but can be leveraged for computational enhancement.
• The developed GPU-accelerated framework provides a scalable and accessible tool for advancing probabilistic computing research.
• This work paves the way for novel optimization applications in diverse scientific and engineering fields.