Development of Self-Aligned Top-Gate Transistor Arrays on Wafer-Scale Two-Dimensional Semiconductor

Two-dimensional semiconductor materials (2DSM) effectively mitigate the short-channel effect due to their atomic thickness, offering significant advantages over traditional silicon-based materials, particularly in short channel length. In manufacturing 2DSM top-gate field-effect transistors (TG-FETs), simultaneous miniaturization of the gate and channel can only be achieved through a self-alignment process, enabling high-density integration of short-channel FETs. However, current self-aligned FETs based on 2DSM face challenges in attaining wafer-scale integration due to manufacturing process limitations. This work has successfully developed high-performance and wafer-scale TG-FET arrays using a self-aligned method that integrates the processes of dry etching, wet selective etching, and post-device optimization. The miniaturization is demonstrated by fabricating TG-FETs with a channel length of 200 nm, achieving an impressive on-state current density of 465.5 µA µm^-1 and a high on-off current ratio of 10⁸. Furthermore, we constructed the inverters and logic modules based on self-aligned FETs, showcasing the process's compatibility for future integration.