SAluMC: Thwarting Side-Channel Attacks via Random Number Injection in RISC-V.

Area of Science:

• Computer Architecture
• Cybersecurity
• Hardware Security

Background:

• Processor performance advances have made caches critical, increasing sensitive data storage and user security concerns.
• Hardware vulnerabilities, unlike software threats, are difficult to detect and fix, with side-channel attacks posing a significant risk.
• Side-channel attacks exploit hardware, bypassing software security to steal data from components like caches and registers.

Purpose of the Study:

• To propose a novel architecture for the arithmetic logic unit (ALU) and memory controller (MC) to mitigate side-channel attacks.
• To enhance hardware security in computer systems without significant design overhead.
• To provide a robust defense against emerging hardware-based threats.

Main Methods:

• Developed a new RISC-V based microarchitecture for the ALU and MC.
• Integrated hardware-generated random numbers into the architecture.
• Focused on minimal design costs, seamless integration, and ease of modification.

Main Results:

• The proposed architecture effectively mitigates side-channel attacks.
• The design demonstrates minimal impact on the original system structure.
• The approach offers a cost-effective solution for hardware security.

Conclusions:

• The novel RISC-V architecture provides an effective defense against side-channel attacks.
• The design is practical due to its minimal cost and integration ease.
• This approach enhances the security of sensitive information in modern electronic devices.