Hardware-efficient quantum error correction via concatenated bosonic qubits

Area of Science:

• Quantum Computing
• Quantum Error Correction
• Superconducting Circuits

Background:

• Quantum computers require quantum error correction for practical applications, but current methods have high physical qubit overhead.
• Hardware-efficient approaches are crucial for scaling quantum computing.

Purpose of the Study:

• To realize a logical qubit memory using concatenated bosonic codes for improved hardware efficiency.
• To investigate the performance and scaling of this new error correction strategy.

Main Methods:

• Utilized a superconducting quantum circuit to implement concatenated bosonic cat qubits with an outer repetition code (distance d=5).
• Employed a stabilizing circuit for passive protection against bit flips and ancilla transmons for phase flip correction.
• Demonstrated a noise-biased CX gate for cat-transmon systems to suppress logical bit-flip errors.

Main Results:

• Achieved a logical qubit memory with a phase-flip correcting repetition code operating below the error threshold.
• Demonstrated suppression of logical bit-flip errors with increasing cat qubit mean photon number.
• Measured minimum logical error rates of 1.75(2)% for distance-3 and 1.65(3)% for distance-5 codes.

Conclusions:

• Concatenated bosonic codes offer a hardware-efficient path to fault-tolerant quantum computation.
• The intrinsic error suppression of bosonic encodings is key to using efficient outer error-correcting codes.
• This approach shows promise for building scalable and robust quantum computers.